memory design for a 10 by 10 matrix in VHDL

[ammassk]

Dear all

I have real number's in a text file which is stored in the form of 10 by 10 matrix. I need to store this values in a LUT. After doing this I need to make two separate memory for magnitude of all these values and sign for all real values.Which type of RAM I have to use for storing these values for implementing this in FPGA?
Can anybody give VHDL code of memory for this?

 

[TrickyDicky]

first of all you wont be using real numbers. You will be using floating point via 32 bit std_logic_vectors. So if you need a 10x10 matrix you'll need a 128x 32bit ram. This is pretty easy. Unless you're trying to access all 100 values simulataneously, where I suggest you start reading up on digital logic.

 

[ammassk]

This is pretty easy. Unless you're trying to access all 100 values simulataneously, where I suggest you start reading up on digital logic.

I didnt understand what you mentioned in this. Please give me a clear idea about this

 

[mrflibble]

What he means is that for your 10x10 matrix you will need a RAM with 128 entries, 32-bit wide. The implementation of which should be easy enough.

 

[ammassk]

What he means is that for your 10x10 matrix you will need a RAM with 128 entries, 32-bit wide. The implementation of which should be easy enough.

Thank you. But sir actually I asked the real to floating point conversion regarding. Is there any sample code available for this?

 

[mrflibble]

Is there any sample code available for what? Could you try to rephrase the question so as to prevent us having to guess what that was supposed to mean?

 

[TrickyDicky]

Have youi analysed your problem fully? do you really need floating point? FP is expensive to implement in FPGA with large latency. have you investigated fixed point?

 

[ammassk]

my problem is to store all these real values in a memory.So I need to do file read operation, real to bit vector conversion and a memory.Here I am asking for the conversion of real to bit vector. I need code for this conversion sir

 

[TrickyDicky]

You would not need to convert to a bit type, because if you sent the values from a PC they would already be in a 32 bit IEEE format. Real types are not suitable for synthesis. They are for simulation or setup values only.

 

[ammassk]

ok sir. My input values to the decoder are real values. These are not synthesizable. Then how can i implement these decoder in FPGA?

 

[TrickyDicky]

How are they send from a PC? if they are sent via from the PC in real time, they would just be 32 bit values. If they are constant, they can still be 32 bit values. You dont have to use the real type (but you will have to use floating point IP cores)

 

[ammassk]

thank you sir. I will try