24-bit width input data converted to 32-bit width data

Hello everybody:

I want to capture the input data and store them into SRAM. The Width of the input data is 24-bit at a speed of 50MHz, but the SRAM input data width is 32-bit. So, how can I do? I put forword the following solutions:
1) Using serials-in-parallel-out (SIPO) and PISO. Capture the data every 4 clock cycles and register to data_temp (95 downto 0). Then store to SRAM in 3 write clock cycles.
2) Using FIFO. But how to set the hand-shake signals?

Is there any other better solutions，or tips or document?

Thanks. Wish everyone happy every day:smile::smile:.

i guess you can append 0's to the MSB and then write to the SRAM. In this way ur original data would also remain the same.

vaisram said:

i guess you can append 0's to the MSB and then write to the SRAM. In this way ur original data would also remain the same.

Click to expand...

Thank you for you reply. Indeed, after storing the input data to SRAM, I need read the data out with width of 32-bit. If add '0' to MSB, it will produce error except of the conversion of 24-bit to 32-bit.

If you know you added '0's when you wrote it, cant you just strip out the '0's when you read it?

TrickyDicky said:

If you know you added '0's when you wrote it, cant you just strip out the '0's when you read it?

Click to expand...

Thanks. what I mean is ,for example, the sram write data is data_wr[31:0]={0000,0000,valid data}. But in fact, I want the read data is data_rd[31:0]={all valid data}. how can i get it?

My original question is how can I convert the data_in[23:0] to data_wr[31:0] with all valid data bits and then write to SRAM. If using FIFO, how to connect hand-shake signals?

thank you again.

Why do you want to make all 32 bits valid data? If your read and write clocks are the same frequency its going to be much more bother that its worth, but may be worth it if you have different clock frequencies. But you will need a packer and unpacker, because the data is going to end up looking like this:

(letter is word, number is byte number)

Memeory Address
A1 A2 A3 B1 0x0000
B2 B3 C1 C2 0x0001
C3 D1 D2 D3 0x0002
.... etc.


Basically, its not a very friendly packing scheme. Try and keep it as simple as possible.

Hi TrickyDicky:

thank you for your reply. I think I understand you. I describe my project as below, and look for your advice.

I use FPGA to acquire the input data which is 24-bit width at a frequency of 50MHz. But the data must be provided to another module with 32-bit data width. I use two on-board SRAM to buffer the data as a ping-pang manner. I think if I can convert the 24-bit to 32-bit, so the read sram operation will be easier. Do you have some good ideals? I searched the internet and It seems FIFO can do. But how can I decide when to read and write the fifo,or do you have some examples?

thanks a lot.

The big question is how is the 24 bit and 32 bit data formatted? Without that knowledge you're not going to get very far.

TrickyDicky is right.

You don't need to convert as such. If you add '0' at the beginning, between each byte or at the end (depending on what you want to achieve), you have converted your 24bit to 32 bit.

You need to use the 24 bits input data in the start of the 32 bit data and fill the rest with 0.
Its like having a 10 bit a/d converter, when you want 8 bits you read only the 8 MSB bits and you discard the 2 LSB, if you use only the 8 LSB then you max reading will be 1/4 of actual max.
In your case if you copy your 24 bit data to the LSB and fill the first 8 bits with 0 then you can only have a max value of 1/256 of the max 32 bit value.
Like the above example consider a 32 bit A/D converter, when you want 24 bit resolution you need to read the 24 MSB and discard the last 8 bits, so this is exactly the bits you need to fill with your 24bit input.

Alex

---------- Post added at 14:24 ---------- Previous post was at 14:09 ----------

You can also do oversampling but the resulting sampling frequency will be very low.
For 25 bits resolution you need to add 4 24bit samples and shift right 1
For 26 bits resolution you need to add 16 24bit samples and shift right 2
For 27 bits resolution you need to add 64 24bit samples and shift right 3
For 28 bits resolution you need to add 256 24bit samples and shift right 4
For 29 bits resolution you need to add 1024 24bit samples and shift right 5
For 30 bits resolution you need to add 4096 24bit samples and shift right 6
For 31 bits resolution you need to add 16384 24bit samples and shift right 7
For 32 bits resolution you need to add 65536 24bit samples and shift right 8

so the sampling frequency for the 32 bit will be 50000000/65536=762 Hz

Alex

---------- Post added at 16:05 ---------- Previous post was at 14:24 ----------

One more note, if you are using the absolute value of the 24bit data (for example a counter result) then you need to copy the value to the lower bits of the 32 bits data so that the value is exactly the same.
On the other hand if you want to transfer your measurement as a percentage of the max value from the 24bit domain to the 32 bit domain then you copy the data to the upper 24 bits.

Alex

Hi Alex:

Thanks for your reply once and again.

Your answer is very clear. I think it is correct under the situation of data acquisition,especially samping the AD convertor. But under some special situation, maybe there are some other methods. if you are interested in the subject, you can check the attached pdf document and maybe it can some suggestion.
what about your opinion?

Thank you.

Ok, now i got what you want to do, you want to fill the 32bits with 24bit data so that you can fit more data in the ram.
I have dove something similar with a 10bit A/D and wrote the data to a 16 bit sram.

what i did was
Read the first sample and copy the data to ram D15-D6 pins
Read the second sample and copy the first 5bit data to ram D5-D1 pins
strobe the ram to write data
copy the rest 5bit data to ram D5-D1 pins
Read a new sample and copy the data to ram D15-D6 pins
strobe the ram to write data
and start from beginning
I was not using D0 so that the data positions were in the same bits every 3 times so it was easier to read.

You are using 24bit in 32 so 24+12 is not an option.
I'm thinking how it could work

24+24=48 -32(write) =16 bits left unwritten
16+24=40-32(write)=8 bits left unwritten
8+24=32-32(write)=0

So you can restart the same cycle every 3 writes, maybe with a state machine.

Alex