Doubt regarding timing analysis

[sharif.shiek]

Hi everybody..

why hold violations are fixed after CTS only, why they don't fixed along with setup violations after placement stage..please clarify my doubt..
thanks in advance..

 

[yadavvlsi]

Setup time equation:
Tcq + Tcomb> Tskew + Thold
Hold time equation:
Tcq + Tcomb<Tskew +T - Tsetup

Setup violation depends on the data path delay while hold violation depends on the clock path delay. Before CTS clock path is taken as ideal. We don't have skew and transition numbers of the clock path. Clock is propagated after CTS that why hold violations are fixed only after CTS.

 

[sharif.shiek]

Setup time equation:
Tcq + Tcomb> Tskew + Thold
Hold time equation:
Tcq + Tcomb<Tskew +T - Tsetup

Setup violation depends on the data path delay while hold violation depends on the clock path delay. Before CTS clock path is taken as ideal. We don't have skew and transition numbers of the clock path. Clock is propagated after CTS that why hold violations are fixed only after CTS.

but before cts also we giving uncertainty in constraints file..what about that?

 

[yadavvlsi]

Clock uncertainty accounts for skew and PLL jitter. But you get exact skew number only after CTS when clock is propagated.

 

[sharif.shiek]

Setup time equation:
Tcq + Tcomb> Tskew + Thold
Hold time equation:
Tcq + Tcomb<Tskew +T - Tsetup

setup hold equations what you said was seems to wrong..
At zero skew
Tcq+Tcomb<= Tclock_period-Tseup //setup
Tcq+Tcomb>=Thold //hold
At possitive skew
Tcq+Tcomb<=Tclock_period-Tseup+Tskew //setup
Tcq+Tcomb>=Thold+Tskew //hold
At negative skew
Tcq+Tcomb<=Tclock_period-Tsetup-Tskew //setup
Tcq+Tcomb>=Thold-Tskew //hold

correct me if i'm wrong...

 

[yadavvlsi]

yes, you are right.!!!

Simply put the skew value with sign in below equations whether it is positive or negative.
Setup time equation:
Tcq + Tcomb> Tskew + Thold
Hold time equation:
Tcq + Tcomb<Tskew +T - Tsetup

 

[sharif.shiek]

Clock uncertainty accounts for skew and PLL jitter. But you get exact skew number only after CTS when clock is propagated.

ok, but why setup is fixing after placement..according you, setup also should be fixed after CTS, but here we fix all the setup violations after placement?..hope you understand my doubt..

 

[yadavvlsi]

Setup timing depends on the data path delay. Data path delay is very much dependent on the placement of cell. Placement also determine net length. First we try to optimize data path and then build a clock tree for optimized datapath. After CTS we get to know actual hold violations. It is not necessary that if you fix all setup violation in preCTS stage and you will not have them in later stage. Routing delay and crosstalk can lead setup degradation that you need to fix in later stage.

 

[sharif.shiek]

Setup timing depends on the data path delay. Data path delay is very much dependent on the placement of cell. Placement also determine net length. First we try to optimize data path and then build a clock tree for optimized data path.

I think setup is also depends on clock path delay, because skew and jitter are clock parameters, those are effect setup timing...correct me if i'm wrong

 

[yadavvlsi]

Ofcourse, skew has impact on setup and hold time both. Positive skew is good for setup and bad for hold. Similarly negative skew is good for hold but bad for setup. We try to optimize skew while building clock tree. Sometime we also use skew for meeting setup and hold i.e called useful skew.

 

[naribtech]

Hi Sharif ,

A simple answer for your question is we can meet the hold easily by adding a delay buffer at nearer to end point. But to meet setup we have to consider all factors like people discussed earlier.

Thanks,
Nari