1Gbit memory addressing with just 24 address lines

[zorax85]

I have to solve the following problem ...
I need to address a 1Gbit memory (with 26 address lines), but the device in charge to do this operation has only 24 address lines. I read somewhere that usually in these cases the problem is solved by using a portion of the data bus in order to decode the address lines "missing", but I have no idea how this thing could be implemented.
Someone could give me an explanation or what I should looking for?

---------- Post added at 11:06 ---------- Previous post was at 10:25 ----------

Just to be clear, between memory and device, I have another device fully connected to the Prom (26 lines), so I think I need a kind of protocol inside this device, in order to decode from 24 to 26 lines.

 

[lucbra]

Maybe you can try to send your address in two words, lower 16 and upper 10. Because you have 24 lines, you could use one of the address lines to decode the upper/lower word.

 

[zorax85]

Maybe you can try to send your address in two words, lower 16 and upper 10. Because you have 24 lines, you could use one of the address lines to decode the upper/lower word.

I don't understand, please could you try with an example?

Thanks.

 

[FvM]

I fear, you didn't clarify the problem. 24 address lines usually indicate a memory space of 16 MByte (or MW respectively). Larger memories can't be accessed continuously and possibly not even assigned to unique logical addresses. You mainly have to refer to the architecture of the respective device (I presume a processor) to understand the available options. Memory banking by additional select lines should be possibly anyway, but the decision depends on the application objectives, that haven't be mentioned at all.

 

[zorax85]

Basically this is the scheme...

 

[TrickyDicky]

for continuous memory access, you willl have to sacrifice 2 data bits.

otherwise, Device B may be able to use multiple cycles to form a full address, but you wont be able to utilise all of the bandwidth.

 

[zorax85]

for continuous memory access, you willl have to sacrifice 2 data bits.

otherwise, Device B may be able to use multiple cycles to form a full address, but you wont be able to utilise all of the bandwidth.

...in the second case you mean use something like a page register?...

But now I'm thinking... maybe I'm lucky because Device A & Device B, use a clock frequency double than the memory, so I could form a 26bit address in 2 clock cycles, and let the memory work normally with the maximum frequency supported (that is half of the one I'm using on others devices).

 

[FvM]

I think, the scheme suggests memory banking. Depending on the application, you have to choose a method how banks are selected by device A. You can either implement a dedicated bank register or use additional signals from device A for bank select. As previously mentioned, apart from being able to select memory banks physically, you should consider how they are represented logically, assuming device A is a processor.

P.S.: I don't understand, how the multiple cycle point is related to the problem. Basically device A is reading or writing single data words with an unique address.