18% layout mismatch of a current mirror

[prcken]

hello
the finger ratio of my current mirror is 4:100, it should have 20mA sink current flow in the mirror leg, but it comes out at 16.5mA by measurement. 18% deviation from simulation results which can not be accepted.
i could not figure out the reason, i checked the layout, only found the layout difference between main leg and mirror leg.
the devices in main leg are layout at seperate style, while the devices in the mirror leg share the source and drain region at the cascoded node for the sake of save silicon area.
please check the attached picture for information.
do you think it is the layout made this 18% deviation of this current mirror?
PS. the current in the main leg comes from banggap and current reference generator circuits, it should be accurate, the current in other blocks seems normal.
thanks
-Kehan

 

[hock]

Re: layout mismatch?

please read document on matched current mirrors, you will find that the transistors are always aligned and are placed very closed to each other so as to minimize thermal gradients.even the entry and exit directional of currents is kept same.

hock

 

[prcken]

Re: layout mismatch?

please read document on matched current mirrors, you will find that the transistors are always aligned and are placed very closed to each other so as to minimize thermal gradients.even the entry and exit directional of currents is kept same.

hock

hock
dont you think the deviation is too much even though the current mirror is not matched precisely?
do you have some examples in terms of numbers and statistics about mismatch?
Kehan

 

[dick_freebird]

layout mismatch?

20% error seems high, but why is M2 channel drawn longer than
the rest? Could you put up a schematic that tells us what's what?

 

[prcken]

Re: layout mismatch?

20% error seems high, but why is M2 channel drawn longer than
the rest? Could you put up a schematic that tells us what's what?

dick_freebird
i am sorry for the looking different in the layout picture, this is due to different zoom in scale when i was doing snapshot.
i attached a schematic of both legs for your information.
-Kehan

 

[jiesteve]

Re: layout mismatch?

Probe the voltages -- there could be some mismatch between diode and mirror legs. Also ensure that cascodes are in saturation

 

[JoannesPaulus]

layout mismatch?

Have you considered "stress effect" and "well proximity effect"? I believe these are responsible for your 20% mismatch, especially if you are using a deep-submicon technology.
Moreover, for good matching, your diode-connected transistors should be somewhere in the middle of your sink devices.

 

[dick_freebird]

layout mismatch?

When I look at the layout plots, the one titled "Separate active
area for M1 and M2" appears to have come from a single layout
display, have same drawn W, but evidently different L.

Cascode structures perform well right up to the point where you
begin to compress headroom. Then they devolve to the same, or
worse fidelity than a bare single-high current mirror. If the
headroom on thr output side is less than the input side, this
might be part of it. You might experiment with other cascode
styles (e.g. Wilson), vary VBIAS to mess with headroom
and so on. For example sweep VBIAS and see how much
(simulated) margin you have between your OP and where fidelity
begins to degrade, at your present output voltage position;
vary output voltage at present VBIAS, etc. This could yield
you some better map of where the cascode works acceptably,
and not.

The model fitting of the transition from linear to saturation is
often not all that well done, and maybe this is also a source of some
error.

 

[elevenak]

layout mismatch?

Hi, guys. I am a layout designer.
I can not believed why layout designer place cascode device like that.
For example: M1=15/0.35 m=4 M3=15/0.35 m=100 M2=15/0.6 m=4 M4=15/0.6 m=100.
set A=(M1 M2 M2 M1), B=(M4 M3 M3 M4)
so, we place as below:
Dummy 13B A 12B B(dummy) Dummy
Dummy B(dummy) 12B A 13B Dummy
We can share all transistors source and drain together.
About 18% mismatch, i think it cause by seperating M1 M2 from M3 M4.

 

[prcken]

Re: layout mismatch?

yep, the main leg should be placed into the sink leg. i am going to change the layout according to rule.
i just can not believe the mismatch can up to 18% or so!
i will report to your guys once i get the measured results after the change. (at least 2 months later)
thank you all.
-Kehan

 

[Linvo]

Hello!
What is your technology? What is the minimal channel length? May be 0.35um is too small for mirror transistor length channel?
Could you report results and new topology version, please?

 

[Sergiu_Q]

Re: layout mismatch?

elevenak I'm totally agree with you.
STI can introduce a mismatch ,metal stress also but the placing of mirror "diode" is totally wrong .
18% mismatch is quite much but looks it is possible.