Small delay defects (SDD)

[anjana_das]

Hi,

What is Small Delay Defects ( SDD ) . How does it differ from Transition fauts? How are these SDD handled /detected in the latest ATPG tools???

Regards
Anjana

 

[vlsi_eda_guy]

Small Delay Defect actually tries to capture faults which are very small in magnitude. If you understand transition fault then you will agree that a fault will be detected if and only if it bigger then the slack available on the path on which it is detected.

For example lets take a fault of magnitude 2ps also assume that this fault is detected on a path with available slack of 5ps. So, even if this fault does come on a fabricated chip the patterns will pass. But at the same time this 2ps fault comes on a critical path with available slack of 1ps then the chip is going to fail but the patterns will pass.

Now the current ATPG tools in transition tries to detect the fault on the shortest path that is with maximum slack , but if we some how target the same fault on the longest path i.e with least slack then the chances that even the small fault will get detected when on ATE.

I hope I was able give you some idea to get going....

 

[anjana_das]

Hi vlsi_eda_guy,

Thanks a lot for the clear explation on SDD. But I have one more doubt.

"Now the current ATPG tools in transition tries to detect the fault on the shortest path that is with maximum slack , but if we some how target the same fault on the longest path i.e with least slack then the chances that even the small fault will get detected when on ATE. "

The "longest path" that you have talked about, does it need to be a critical path ? Or does it mean the longest path having the target faut in it and this longest path may not necessarily be a critical path of the design??

Thanks
Anjana

 

[vlsi_eda_guy]

yes you are correct , the longest path may or may not be a critical path. All the faults cannot be propogated on the critical path.

This longest path will be specific to each fault and will be the path with least slack on which this fault can be detected

 

[anjana_das]

Hi vlsi_eda_guy,

Thanks for the explanation. Now my doubt has been cleared.