100V Floating MOSFETs

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shepst

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Hi all,
I'm trying to understand whether it is possible to "float" a circuit?
How can I manage doing that?
the circuit is combined with 5v pmos and 5v native nmos.
the VDD suppose to be 100V and VSS 95V
the voltage drop over all mosfets is around 5V (Vds, Vgs)
if I use deep N-Well all around the circuit, will it stand the high voltage?
how can I calculate the breakdown voltage of the DNW?
 


Sure, you can do that, if you connect the substrate to DVSS, and if you consider that the whole circuit (incl. substrate and package) is not isolated from DGND.

In this case the deep N-Well has just to withstand a voltage of DVDD-DVSS=5V .

If you'd want to connect the substrate to DGND instead, you'd need a special HV process which use SOI or a HV epi substrate, usually with structure sizes > 1µm , see e.g the following flyer: View attachment XDH10_Data_sheet.pdf or this paper: View attachment HV_CMOS_Level_Shifter.pdf.


shepst said:
how can I calculate the breakdown voltage of the DNW?
Click to expand...

This is published by the fab/foundry. Calculation can be done if you know the doping concentration of the DNW at its junction.
 
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    shepst

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okay, thanks for the answer.
do you know if there's any problem with the floating 5V mosfet, while it gets high voltage (of 100V)?
I mean drain or source voltage, or the risk is only depends on voltage drop between drain to source(or opposite)?
 

If you think of the floating substrate method (substrate=DVSS) you should be aware that the whole circuit incl. its pins & its package is on HV, i.e. the common HV precautions against touching and PCB connectivity insulation must be taken.

For the MOSFETs themselves there should be no problem, as the whole circuit only sees the normal 5V supply voltage. But you should also take precaution to limit DVDD-DVSS ≤ 5V by external provision (e.g. Z-diode limitation).
 
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