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1.25 GHz LVDS-like buffer

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Nixphe

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Hello,


i'm currently designing a 1.25GHz (digital signal) LVDS-like driver to drive an FPGA. Could someone please help me or advise me on the following choices:
- could i avoid internal termination of the transmission line, and hence reduce power consumption for a given swing by half? Assuming rise/fall time of 1/10th of period, i guess i would have an analog bandwidth of approx 5GHz or a wavelength of 3cm in free space, approx 1cm in FR4. My traces will be beyond that for sure.
- should i think of appropriate common mode termination also? If i do so ... as i'll probably end up with tightly coupled differential transmission line-pairs, which would render the common-mode characteristic impedance smaller then the differential mode one, clean termination gets more difficult, i think. If I should work on such a termination, what common-mode characteristic impedance may i expect when keeping the differential one on 100 ohm (2*50), on FR4 and e.g. when connecting BGA's and having quite of a few of those pairs?

Big thanks for your input!

Kind regards
 

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