Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

What is the Stratix startup time ?

Thread starter kobik
Start date Jul 22, 2003

Status: Not open for further replies.

Jul 22, 2003

#1

K

kobik

Member level 3

stratix startup time

hi,

how much time will take to stratix 1s30 with epc16
from power up to finish loading (not include POR)

thx,
kobik

Jul 22, 2003

#2

Phytex

Member level 4

Normally max.

Hi,

I don't think exactly how long a single device needs to startup, but normally it have to finish after max. 400ms!

Phytex

Status: Not open for further replies.

Similar threads

A
How can I run verilog code with data at a specific time in the past?
- Started by alexis57
- Jan 28, 2024
- Replies: 2
PLD, SPLD, GAL, CPLD, FPGA Design
L
Delay Line Time To digital Converter
- Started by Lizwi
- Mar 3, 2024
- Replies: 3
PLD, SPLD, GAL, CPLD, FPGA Design
R
A way to reduce simulation time
- Started by Raeiu
- Feb 2, 2024
- Replies: 9
PLD, SPLD, GAL, CPLD, FPGA Design
M
How to instantiate another vhd file inside testbench, where the testbench is used for opening files
- Started by metamisers
- Jan 6, 2024
- Replies: 6
PLD, SPLD, GAL, CPLD, FPGA Design
K
What's the difference between RAM and ROM with a coe files in Xilinx FPGA?
- Started by kevinwang65
- Mar 11, 2024
- Replies: 13
PLD, SPLD, GAL, CPLD, FPGA Design

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.

Accept Learn more…

Top