cheesyfeet
Newbie
I have managed to place and route a ROM macro, however have issues when running verifyGeometry. This throws violations due to 'Short Violations' between the signal nets of the routed tracks and the blockage of the ROM. This only occurs on certain pins. On investigation, these pins are the input pins, with size (0.5x0.5) - the output pins of size (2x0.5) do not throw errors.
I think that the problem is that the signal tracks are of width 0.6, which means that the track exceeds the pin area and causes a violation. I tried to reduce the track width using a NONDEFAULT rule, however it appears that 0.6 is the minimum for the technology (ams C35B4) so throws errors when I try to route. The ROM is generated for the C35B4 tech, so i'm not sure why the pins are below min size, but does anyone have any ideas how this can be rectified? My thought was to try and instruct nanoRoute to not overlap the pins (ie. abut the signals to the pins and stop as soon as touching, thus not overlapping the OBS layer) but I'm not sure if this is a good idea or how to tell the router to do it.
Violations on side of macro:
Close up of violation on single pin (error message at bottom):
I think that the problem is that the signal tracks are of width 0.6, which means that the track exceeds the pin area and causes a violation. I tried to reduce the track width using a NONDEFAULT rule, however it appears that 0.6 is the minimum for the technology (ams C35B4) so throws errors when I try to route. The ROM is generated for the C35B4 tech, so i'm not sure why the pins are below min size, but does anyone have any ideas how this can be rectified? My thought was to try and instruct nanoRoute to not overlap the pins (ie. abut the signals to the pins and stop as soon as touching, thus not overlapping the OBS layer) but I'm not sure if this is a good idea or how to tell the router to do it.
Violations on side of macro:
Close up of violation on single pin (error message at bottom):