ashrafsazid
Advanced Member level 4
Hi,
I am designing a PMOS LDO using indirect miller feedback. I see that the minimum PSRR is sufficient for high capacitive load (100n). But when the load is reduced to 10p then the minimum PSRR drops to zero. I do not get any explanation regarding this issue in textbook.
(I used the indirect miller feedback such that it does not couple with VDD line at high frequency. i.e, with the nmos cascode load)
Could anybody please give a reasonable explanation?
Thanks.
I am designing a PMOS LDO using indirect miller feedback. I see that the minimum PSRR is sufficient for high capacitive load (100n). But when the load is reduced to 10p then the minimum PSRR drops to zero. I do not get any explanation regarding this issue in textbook.
(I used the indirect miller feedback such that it does not couple with VDD line at high frequency. i.e, with the nmos cascode load)
Could anybody please give a reasonable explanation?
Thanks.