Hugo17
Junior Member level 1
I do have a sdc-File with following time constraints:
After running the TimeQuest I get following waveform output to one data input to the FPGA .
Question:
With which time constraint I can reduce the Data Delay time (4.316ns)? :?:
Thanks in advance
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
# Create Clock
#**************************************************************
create_clock -name {i_clk} -period 8.000 -waveform { 0.000 4.000 } [get_ports {i_clk}]
create_clock -name virt_clk -period 8.000
derive_clock_uncertainty
set_input_delay -clock virt_clk -min 1.4 [get_ports i_data[*]]
set_input_delay -clock virt_clk -max 5.4 [get_ports i_data[*]]
After running the TimeQuest I get following waveform output to one data input to the FPGA .
Question:
With which time constraint I can reduce the Data Delay time (4.316ns)? :?:
Thanks in advance