AllenD
Member level 5
Hello team
I am trying to build a clock generator in CMOS circuit. The clock generator circuit has one ideal input clock and will output several clocks of different phases, duty cycles and period, which is desired by my switched capacitor circuit clock. The clock generator was designed based on Johnson counter.
I have one problem. There is a little phase error between 2 of the output clocks from the clock generator. I believe the phase error was due to the parasitics in the clock generator (the clock freq is pushing to the limit of the CMOS process that I am using).
I wonder if there any way I can insert a controlled delay in the clock generator to compensate the phase error?
Because this is clock generator, I assume I can't use a sample and hold to controlled delay.
Can anyone help me?
Thanks
Allen
I am trying to build a clock generator in CMOS circuit. The clock generator circuit has one ideal input clock and will output several clocks of different phases, duty cycles and period, which is desired by my switched capacitor circuit clock. The clock generator was designed based on Johnson counter.
I have one problem. There is a little phase error between 2 of the output clocks from the clock generator. I believe the phase error was due to the parasitics in the clock generator (the clock freq is pushing to the limit of the CMOS process that I am using).
I wonder if there any way I can insert a controlled delay in the clock generator to compensate the phase error?
Because this is clock generator, I assume I can't use a sample and hold to controlled delay.
Can anyone help me?
Thanks
Allen