Can anyone explain why two DFF can decrease the possibility of Metastability?

1、The main way to solve the Metastability is to add a reg as a synchronizer after sampling reg

my understanding is here, please correct:
after a long enough time, the invalid signal sampled by the sampling reg will return to an effective level, and then the synchronizer reg can take this effective level.

But returned level may be 0 or 1, then although the synchronizer reg sampled the level. That may also lead to a logical error, then what is the meaning of using the synchronizer?

2、why use two reg as synchronizer？

Thank you

But returned level may be 0 or 1, then although the synchronizer reg sampled the level. That may also lead to a logical error, then what is the meaning of using the synchronizer?

2、why use two reg as synchronizer？

Click to expand...

Metastability occurs if the level change occurs at the sampling clock edge. Sampling 0 or 1 would be equally correct in this situation. A problem occurs if the sampling register hasn't yet settled to 0 or 1 after a clock cycle when the data is processed by the sink. Sampling the register output by a second (or possibly further by third) register can reduce the probability of getting still neither 0 or 1 at the final output to a miniscule number.

Thanks for you reply.
what i mean is that. I expect the output should be 0, however after a Metastability occuring the output is settled. But it may settle to 0 or 1. if it's 1, it'll lead to logic error.

Sorry, that's na error of reasoning. Metastable events can only occur if a signal edge falls into the register's setup and hold window. In this case you can't know in advance if you sample the old or the new value.

wyn2252128 said:

Thanks for you reply.
what i mean is that. I expect the output should be 0, however after a Metastability occuring the output is settled. But it may settle to 0 or 1. if it's 1, it'll lead to logic error.

Click to expand...

On a CDC you should not have to know or even need to know if a signal will be a certain value at a specific clock cycle. If you have that kind of requirement then you don't have a good grasp of proper CDC design. The whole point of a CDC circuit is to reduce the probability of a metastable event propagating into the new clock domain causing problems where multiple sinks see different values of the CDC signal.

If a start signal crossing clock domains is still metastable on the last register of the synchronizer and that signals goes to two different FSMs, then there is a probability that one FSM will see this metastable signal as a 1 and the other will see it as a 0. Now those FSMs are out of sync. This was a real world problem that I had to debug as a consultant, the engineer that wrote the code didn't understand the need for CDC crossing FFs and the design only worked on the bench with one specific lot of parts, some would fail at very cold temps some would fail at high temps. All of the problems were due to race conditions between the two FSMs seeing the start control signal.

So to summarize the CDC occurs first and then synchronized output can be examined for a 1 or 0.
If the CDC input was transitioning from 0-1 then the output could be either 0-0 or 0-1.
If the CDC input was transitioning from 1-0 then the output could be either 1-1 or 1-0.
In either case the end result will be a transition that has a variable delay before the output transitions.

Modern logic families, unlike the old TTL type parts, typically don't exhibit really bad behavior like runt pulses on their outputs when going metastable. Once you've seen something like that coming out of a FF you really want to add 3 or more FFs following that one to make sure that doesn't end up in your new clock domain ;-)

If you look closely at the DFF output behavior as you
go from hold to setup in a very fine stepping, you will
see the CK-Q delay stretch out, then a narrow plateau
where the pulse "stalls" in the middle, and then then
try and revert, and then show no capture of the intended
D value. Real "metastability" is where the FF never makes
it to a valid logic state, or fails to do so within the inter-
clock period.

The second DFF's regenerative gain will make a decision
based on level or noise, except with a very small window
of uncertainty. To fail you need the first FF to be "undecided"
(which is different than "uncertain", the basis of setup /
hold window limit setting) when the second FF's clock
arrives, and for that "indecision" to be at a level that
the second DFF can't resolve one way or the other (of
course getting the "right" answer is preferable, but wrong
or right are preferable to "umm...".

There's no such thing as 0% probability of a 2-stage
scheme failing metastable, but the statistics are squared
(odds of first stage metastable at clock2, times odds of the
metastable output voltage being unresolvable for DFF2).

Of course this is all "analog-y" and you may have to
"stay between the lines" and believe what library logic
models and rules tell you.