Ashish Agrawal
Member level 3
Hi Experts,
Can this circuit be used as a flop?
Basically, I have delayed the clock signal and ANDed it with the original clock signal. The output of AND is used as Enable to latch. So instead of having the Enable high for long duration, it will be equivalent to delay of BUFFERs.
If we are able to provide delay of BUFFERs equal to setup time of latch ( setup time will be measured with respect to negative edge/closing edge) then will this circuit work as an edge-triggered flop?
Is it really possible to provide this exact delay? If not, why?
Regards,
Ashish
Can this circuit be used as a flop?
Basically, I have delayed the clock signal and ANDed it with the original clock signal. The output of AND is used as Enable to latch. So instead of having the Enable high for long duration, it will be equivalent to delay of BUFFERs.
If we are able to provide delay of BUFFERs equal to setup time of latch ( setup time will be measured with respect to negative edge/closing edge) then will this circuit work as an edge-triggered flop?
Is it really possible to provide this exact delay? If not, why?
Regards,
Ashish