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edge detection on an asynchronous signal

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flyingmonkey1

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Hi all,
In my design I'm looking for glitches on a test signal (ie signal goes |==|_|===| when it should go |======| if that made any sense :-D). Anyway I was using the following code 

Code Verilog - [expand]
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module positive_edge_detector(
    input clk_in,
    input signal_in,
    output out_edge
    );
 
reg signal;
 
always @ (posedge clk_in) begin
    signal <= signal_in;
end
 
assign out_edge = signal_in & (~signal);
 
endmodule

well anyway this works fine when the clk_in is faster than the glitch in the signal however its not able to detect an edge when the glitch is smaller than the clock period. Is there a better way to be doing this? Thank you
 
Last edited by a moderator:

You could use a toggle synchronizer on the input signal.

Code: 
always @ (posedge signal_in) begin
    t <= !t;
end

always @ (posedge clk_in) begin
    t1 <= t;
    t2 <= t1
end

assign out_edge = t1 ^ t2;
 
Hi,

As long as the "glitches" high phase is longer than a system_clock_cycle you can be sure to detect each single pulse.

If you want to detect shorter pulses, then you need to treat the signal as a clock_input.
Maybe use a DFF with async_clear. DFF_clk is glitch_signal, DFF_D is 1.

Klaus

- - - Updated - - -

Added:
I just see that FvM's solution is similar, but it needs no external clear.

Klaus
 

Awesome guys it works well! Thank you very much!
 

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