shaiko
Advanced Member level 5
Hello,
Consider clock domain crossing of a single signal without a dual stage synchronizer.
The sampling domain captures the signal just when it changes and the DFF goes meta-stable.
The Q pin of that DFF feeds a large block of combinatorial logic.
Now, the metastability condition "eats" away some of the timing budget that could have belonged solely to the combinatorial logic - essentially decreasing Fmax.
But if we know that our design runs at a VERY low speed or/and the combinatorial circuit is VERY small - we need not worry about meastability in this case.
would you agree ?
Consider clock domain crossing of a single signal without a dual stage synchronizer.
The sampling domain captures the signal just when it changes and the DFF goes meta-stable.
The Q pin of that DFF feeds a large block of combinatorial logic.
Now, the metastability condition "eats" away some of the timing budget that could have belonged solely to the combinatorial logic - essentially decreasing Fmax.
But if we know that our design runs at a VERY low speed or/and the combinatorial circuit is VERY small - we need not worry about meastability in this case.
would you agree ?