asic_learner
Newbie level 5
Signals with multiple drivers
Hi everyone,
I'm having a doubt.
Why signals with multiple drivers should be wires only, why can't they be reg or logic while declaring signals in verilog?
Thanks in advance
Hi everyone,
I'm having a doubt.
Why signals with multiple drivers should be wires only, why can't they be reg or logic while declaring signals in verilog?
Thanks in advance
Last edited: