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info on timing corners is required

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viswanadh_babu

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Hi All,

Below is the information on various timing corners for which , i must close the timing.

Corner Voltage (V) Temperature (C) Process
BCCOM 0.99 0 FF
LTCOM 0.99 -40 FF
MLCOM 0.99 125 FF
NCCOM 0.9 25 TT
WCCOM 0.81 125 SS
WCLCOM 0.81 -40 SS
WCZCOM 0.81 0 SS

i wanted to know which corner is the worst of all and best of all and why?
what is the relation between delay and temparature ?
Bcz, when i tried worked previously, i have closed the timing for 3 corners simply and delay increases with temparature in worst case. But, now i have 3 corst case corners with different temparatures. But, the delay seems to be more in WCL , even though the temp. is less when compared to remaining two corners. Please calirfy my doubts.
Regards,
K.VISWANADH BABU
 

Hi All,

Below is the information on various timing corners for which , i must close the timing.

Corner Voltage (V) Temperature (C) Process
BCCOM 0.99 0 FF
LTCOM 0.99 -40 FF
MLCOM 0.99 125 FF
NCCOM 0.9 25 TT
WCCOM 0.81 125 SS
WCLCOM 0.81 -40 SS
WCZCOM 0.81 0 SS

i wanted to know which corner is the worst of all and best of all and why?
what is the relation between delay and temparature ?
Bcz, when i tried worked previously, i have closed the timing for 3 corners simply and delay increases with temparature in worst case. But, now i have 3 corst case corners with different temparatures. But, the delay seems to be more in WCL , even though the temp. is less when compared to remaining two corners. Please calirfy my doubts.
Regards,
K.VISWANADH BABU

What's the basis of that observation ?
 

In general, with my experience, I have seen worst corner in the following condition - WCCOM 0.81 125
Best case will generally be BCCOM 0.99 0 FF. Try doing PnR with following settings if you dont have MultiMode Multi Corner flow for your design.

Then , if timings go out of control, then you can think of changing the corners.

Also In general, with increase in temperature, delays increase and hence we have worst corner at maximum operating temperature.

Regards,
R.Srideepa
 

Hi VISWANADH,

In 65nm , 45nm and below technologies the worst delays are seen in "WCLCOM 0.81 -40 SS". This corner is also called as MAX_LT(LowTemp) corner. You can google for "Effect of Temperture Inversion in CMOS" and you will get know the reason for higher delays in this corner.

Ref:
Alpesh Kothari: Temperature Inversion. Is this a new 45nm effect?

Regards,
 
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