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Help: Implement design warnings (FPGA)

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avd

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Hi all,

Can anyone possibly help. When I run the 'Implement design' process in Xilinx ISE4,2i, I get 2 warnings. Can anyone tell me why? They are:

WARNING:Route:48 - The signal "VCC" has no driver so was not routed.

WARNING:par:69 - Option "-xe" overrides some effects of "-ol".

Thanks,
Andrew
 

for the first warning it seems that you had declar a signal called "VCC" and you did not assign logic '1' to it.
 

be alert to your synthesis style.
par -xe is your extra effort level.
par -ol is your effort level.
 

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