selective SDF annotation in a SoC

sdf backannotate+configuration file

I am new on doing this. I need to do a kind of selcetive back annotation for a SoC for gate level simulations. This is using VCS tool.

The point is that we have digital and analog modules, and i have a netlist and sdf file compraising all the design since they come after P&R. Also we have some BFMs on our Test Env replacing some real modules. The issue is that when compiling I get several errors from the annotation part saying that several modules don't match for the sdf. And of course the simulation dosen't go through.

I am wondering if somebody knows a clean way to selectivally enable/disable the back-annotation of each sublock in a SoC and/or enable disable the timing checkings.

I am wondering what to use either some plusargs for VCS tool or to request the SDF file modification from the guy that generated the Netlist and SDF files....

Thanx in advance...:::

enable vcs plusargs

There are two methods to selectively disable/enable timing checks for a module. One method is using a configuration file to achieve this and the second one is using UCLI prompt to achieve this.

You can refer the below SolvNet articles for solutions.

Using configuration file:
https://solvnet.synopsys.com/retrieve/001016.html

Using UCLI command tcheck:
https://solvnet.synopsys.com/retrieve/021981.html

Hope this helps in resolving your issues.