Sujith_Raj
Newbie level 1
Hi all;
I write a VHDL code below. There are no error when I compile it, but then fatal error occur when I try to simulate.
I write a VHDL code below. There are no error when I compile it, but then fatal error occur when I try to simulate.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 library ieee; use ieee.std_logic_1164.all; entity comparator2 is port ( A, B: in std_logic_vector(1 downto 0); Equals: out std_logic); end comparator2; architecture behavioral of comparator2 is begin process(A,B) begin if (A(0)=B(0))and (A(1)=B(1))then Equals <= '1'; else Equals <= '0'; end if; end process; end behavioral;
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