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Error while coding a 2 bit comparator code

Sujith_Raj

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Hi all;

I write a VHDL code below. There are no error when I compile it, but then fatal error occur when I try to simulate.



Code VHDL - [expand]
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library ieee;                                   
use ieee.std_logic_1164.all;            
                                                    
entity comparator2 is port (                    
    A, B: in std_logic_vector(1 downto 0); 
    Equals: out std_logic);                 
end comparator2;                                
 
architecture behavioral of comparator2 is
begin
    process(A,B)
    begin
        if (A(0)=B(0))and (A(1)=B(1))then
        Equals <= '1';
        else
        Equals <= '0';
        end if;
    end process;
end behavioral;

 
Last edited by a moderator:

TrickyDicky

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You dont say what tool or error. There is nothing wrong with the code.
 

vGoodtimes

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is there a testbench? does the tool count the lack of a testbench as a fatal error?
 

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