Junus2012
Advanced Member level 5
Hello,
I have designed simple voltage devider MOS resistor, the circuit is working fine in schematic, with the layout there is no issue, LVS is giving o error. However, in the simulation they are showing very different result, then when I compared the netlist I saw it is different between the schematic and layout, looks like he is mixing between drain and source.
Is it possible to correct to have different netlist if there is not error in LVS ? is there any way to correct it manually ?
Thank you
I have designed simple voltage devider MOS resistor, the circuit is working fine in schematic, with the layout there is no issue, LVS is giving o error. However, in the simulation they are showing very different result, then when I compared the netlist I saw it is different between the schematic and layout, looks like he is mixing between drain and source.
Is it possible to correct to have different netlist if there is not error in LVS ? is there any way to correct it manually ?
Thank you