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Do we use .lib for gate level simulation of netlists?
Hi,
Gate level simulation of what netlist? Where? With what?
You need to give details.
No one can understand what you mean.Are not gate level simulation always done on netlists?
The post was raised for gate level simulation on netlists.
No one can understand what you mean.
Express in detail with correct terminology.
Do you mean Gate-Level-HDL which is synthesized from RTL-HDL ?
After rtls are synthesized using a synthesis tool like Design Compiler of Synopsys, we get a netlist. The simulation of this netlist is called gate level simulation. Is it clear now?
It is Gate-Level-HDL.we get a netlist.
I don’t think he reaches to SDF annotation.You need an SDF file to be simulated with the netlist.
It is Gate-Level-HDL.
I don’t think he reaches to SDF annotation.
Simply his purpose requires standard cell library or technology library.
at a bare minimum, a verilog file of the standard cell library is needed. this should be combined with an SDF, otherwise you get some timing model that is not realistics like a unit delay model (ie, every cells takes 1 time unit to compute its output).
Can a .lib files of a standard cells be used instead of a verilog models of standard cell for gate level simulation?
in theory, yes. lib files do contain the equation of the cell. in practice, no, no simulator that I know of will take a .lib as input
But the equation in .lib may not be similar to the model file. For example if a D-fliplop is taken its behavioural code is understood as a D-flipflop but the equation of it does not reflect the behaviour of a D-flipflop. A LEC tool can read those equations of cells in a .lib if I am not doing any mistake.