shaiko
Advanced Member level 5
Hello,
As far as I know (correct me if I'm wrong), if we declare a variable in Verilog without explicitly giving it a type - it defaults to a "wire".
Is this rule the same with System Verilog ? Or the default is something else ( "logic" for example ) ?
As far as I know (correct me if I'm wrong), if we declare a variable in Verilog without explicitly giving it a type - it defaults to a "wire".
Is this rule the same with System Verilog ? Or the default is something else ( "logic" for example ) ?