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System Verilog - default type of a declared variable

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shaiko

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Hello,

As far as I know (correct me if I'm wrong), if we declare a variable in Verilog without explicitly giving it a type - it defaults to a "wire".
Is this rule the same with System Verilog ? Or the default is something else ( "logic" for example ) ?
 

ThisIsNotSam

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Hello,

As far as I know (correct me if I'm wrong), if we declare a variable in Verilog without explicitly giving it a type - it defaults to a "wire".
Is this rule the same with System Verilog ? Or the default is something else ( "logic" for example ) ?
inputs/outputs in verilog default to wire. variables are the type you declared them to be.
 
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shaiko

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With SV, is there a good reason why not declare all variables and ports as type "logic" ?
 

vGoodtimes

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Verilog has `default_nettype option. this can be added to the top of any files you write. Verilog's default net type is wire and any undeclared variables will be of that type. This made a lot more sense when structural designs were popular. I've only seen `default_nettype none used, so I don't know if you can set `default_nettype logic. Doing so should convert any typos into 1 bit logic.
 

shaiko

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But isn't writing`default_nettype none equivalent to not writing anything at all ?
 

vGoodtimes

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Verilog has an anti-feature that an undeclared name is treated as a wire. Before Verilog2001, this would always be 1 bit. After 2001, the width could be inferred. The intent seems to have been making it easier to connect module instances in a highly structural design.

Because typos get treated as wires, some developers declare `default_nettype none. A side effect of this is that ports now need "input wire" vs just "input".
 
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shaiko

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What do you do in your designs?
Suppose, a signal is indeed logically a wire - do you explicitly declare it as a such?
 

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