feel_on_on
Full Member level 5
design compiler synthesis bottom up vs top down
example : a hierachical design A, top file : my_design.v
include two file : B.v and C.v
Question :
When synthesis , synthesis B.v and C.v individual,then....simply connect them on the top file mydesign.v?
or synthesis directly top file my_design.v ,then......? any suggestion is welcome.
If C.v have two asyn clock, only can synthesis B.v and C.v individually ?
example : a hierachical design A, top file : my_design.v
include two file : B.v and C.v
Question :
When synthesis , synthesis B.v and C.v individual,then....simply connect them on the top file mydesign.v?
or synthesis directly top file my_design.v ,then......? any suggestion is welcome.
If C.v have two asyn clock, only can synthesis B.v and C.v individually ?