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Advantages of SV compared to verilog as a verification point

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aswin123

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how to explain adv's of system verilog as a verification point , compared to verilog verification..........

suggest me..........
 

high level data structue supporting OOP
assertion based verification
 

SystemVerilog -
1. Classes form the base of SV
2. Assertion, randomization and coverage support in same language
3. Separate regions for Testbench and RTL
4. Representation at higher abstraction
5. Fork/join_any,Fork/join_none
6. Final block in addition to initial block
7. interface,clocking block construtcs
and hell lot of feature taken from VHDL, C++, verilog.

thanks
Manmohan
 

system verilog has extensive data type which helps both designer n verification engineer...
verilog is purely for design purpose
shiv
 

Re: Advantages of SV compared to verilog as a verification p

in System verilog verification & design same constructs can be used or different?all are synthesizable code or not???
 

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