xihushui
Member level 2
vhdl procedure
this is a procedure in VHDL,but now i want to change it to a task in verilog.how to do it ? stopBitLength is real,is not a in or out(in fact,it is in),how to do in task of verilog?
procedure sout_chk (
numDataBits : integer range 5 to 8;
Txdata : in std_logic_vector(7 downto 0);
ParityBit : in std_logic;
stopBitLength : real;
parityBitExist : boolean;
constant cycleTime : in time;
signal SOUT : in std_logic) is
variable i : integer;
begin
.......
endtask
this is a procedure in VHDL,but now i want to change it to a task in verilog.how to do it ? stopBitLength is real,is not a in or out(in fact,it is in),how to do in task of verilog?
procedure sout_chk (
numDataBits : integer range 5 to 8;
Txdata : in std_logic_vector(7 downto 0);
ParityBit : in std_logic;
stopBitLength : real;
parityBitExist : boolean;
constant cycleTime : in time;
signal SOUT : in std_logic) is
variable i : integer;
begin
.......
endtask