cippalippa
Member level 2
Hello,
I'm trying to allow some block in a Xilinx Fpga in order to evaluate the necessary size.
I need to know if is possible to set the Xilinx syntetizer to avoid to clear implementation not used yet, for example if I have:
entity prj1 is
port (clk : in std_logic;
d : in std_logic;
q : out std_logic;
datain : in std_logic_vector(3 downto 0)
);
end prj1;
architecture BEH of prj1 is
signal test: std_logic;
begin
strobe_gen: process(clk)
begin
if (clk'event and clk = '1') then
q <= d;
end if;
end process;
test <= datain(3) and datain(2) and datain(1) and datain(0);
end BEH;
The sygnal test for now is unused, I woud like to have in my project the FF and the 4 input AND; if I syntetize with ISE I obtain only a FF.
Thanks for all
D
I'm trying to allow some block in a Xilinx Fpga in order to evaluate the necessary size.
I need to know if is possible to set the Xilinx syntetizer to avoid to clear implementation not used yet, for example if I have:
entity prj1 is
port (clk : in std_logic;
d : in std_logic;
q : out std_logic;
datain : in std_logic_vector(3 downto 0)
);
end prj1;
architecture BEH of prj1 is
signal test: std_logic;
begin
strobe_gen: process(clk)
begin
if (clk'event and clk = '1') then
q <= d;
end if;
end process;
test <= datain(3) and datain(2) and datain(1) and datain(0);
end BEH;
The sygnal test for now is unused, I woud like to have in my project the FF and the 4 input AND; if I syntetize with ISE I obtain only a FF.
Thanks for all
D