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verilog-xl simulation work fine, but ncsim hang up

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eefelix

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Hi,

I've a netlist that when running the verilog-xl simulation, the whole simulation can be finished without problem, but when I put the same netlist into ncsim, the simulation will hang up at the middle of the whole simulation.

Does anyone come across the same problem ? Do you know the reason and how to solve it ? Thanks!
 

eefelix said:
Hi,

I've a netlist that when running the verilog-xl simulation, the whole simulation can be finished without problem, but when I put the same netlist into ncsim, the simulation will hang up at the middle of the whole simulation.

Does anyone come across the same problem ? Do you know the reason and how to solve it ? Thanks!
Click to expand...

did the tool show any error message before it halted?
go discuss this problem with personnel of your EDA support/management department...maybe it's ncsim's own problem (not so well installed or configured)...
good luck!

stan
 

Due to difference between Event-driven and Cycle-driven compile
 

>>>Due to difference between Event-driven and Cycle-driven compile

??? Why ????
----------------------------------------------------------------------------------
NO matter what kind of compilation, the program should NOT hang-up !
----------------------------------------------------------------------------------

I have only met the condition that the simulation can be run successfully
by Verilog-XL, but encounter some Error message(s) in NC-Verilog.
(Of course, you can say it's a tool-dependent problem.
Actually, it's also a coding problem...)

BUT it never hang-up the simulator !
 

agree. doesnt matter if it's event-driven or what. even if two simulators are both event-driven, they could produce different results due to event scheduling timing. however, it should never hang up.

casual3

joe2moon said:
>>>Due to difference between Event-driven and Cycle-driven compile

??? Why ????
----------------------------------------------------------------------------------
NO matter what kind of compilation, the program should NOT hang-up !
----------------------------------------------------------------------------------

I have only met the condition that the simulation can be run successfully
by Verilog-XL, but encounter some Error message(s) in NC-Verilog.
(Of course, you can say it's a tool-dependent problem.
Actually, it's also a coding problem...)

BUT it never hang-up the simulator !
Click to expand...
 

i think that it because of you didn't st you library path correctly,echo your LD_LIBRARY_PATH
 

How to use verilog-xl in C@dence LDV?
I used verilog-xl command "verilog" in LDV3.0.
I can't find command "verilog" in above LDV 3.3 .

Does LDV support verilog-xl above version 3.3 ?
If the answer is "Yes", What's the verilog-xl command above LDV 3.3?
 

run ncsim with -compatibility switch. if it works, then it is like joe2moon said.
 

Oooo...I met the same problem.
Gate-level work fine with 'verilog' command of Verilog-XL, but 'ncverilog' command is hang-up, add '+delay_mode_unit' argument is partial work, but still hang-up on half time of simulation, What's happen?? Use 'verilog' compile spend much time, I don't want.
 

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