Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Reference to create the test bench files for SystemC

Status
Not open for further replies.
S

SivabalanBalasundram

Newbie level 4
Joined
Jun 8, 2006
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,344
Hello..i m a beginner user of systemC .how ever i m familiar with VHDL which i used in a modelsim platform..That why i never used a testbench in VHDL before.Can someone give me some reference which can be very useful for me to learn to create a testbench for me design later in SystemC... Thanks for reading
 

SivabalanBalasundram said:
Hello..i m a beginner user of systemC .how ever i m familiar with VHDL which i used in a modelsim platform..That why i never used a testbench in VHDL before.Can someone give me some reference which can be very useful for me to learn to create a testbench for me design later... Thanks for reading
Click to expand...

Your design is in VHDL this time or SystemC? Assuming it is in VHDL, a simple- trivial testbench will be:

Code: 
entity tb;
end entity tb;
arch.. behav of tb is
.. -- signals
begin
  u0 : dut port map ();

  clk <= not clk after 10 ns;
  stim : process is
  begin
    inp1 <= '1';
    wait for 100 ns;
    inp1 <= '0';
    wait;
  end process stim;
end arch...

This is a pretty bad testbench example, but without any spec, this is what I can show you here in this forum.

Now, if you really want to understand how complex testbenches are built and what suits which domain/block/design, consider taking the 1-day class on "Comprehensive Functional Verification" that my company offers in Bangalore. We have a class coming up in next few weeks, see: www.noveldv.com and send an email to cvc.training <> gmail.com if interested.

HTH
Ajeetha, CVC
www.noveldv.com
 

What is the differnce between systemC and SystemVerilog ?
 

yaseen1 said:
What is the differnce between systemC and SystemVerilog ?
Click to expand...

Depends on whom you talk to - unfortunately. Here are my 2 cents:

1. SystemC is more for modeling, HW-SW simulation etc.
2. SystemVerilog is best suited for Verification

There is some overlap among these 2 in terms of the above said capabilities - SV can do system modeling and SystemC can be used for Verification (via SCV), but the way industry is moving is what I've tried outlining.

Best bet will be - find it for yourself, what tools you have? Refer to: www.systyemc.org and www.systemverilog.org

HTH
Ajeetha, CVC
www.noveldv.com
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top