simulation with SDF uing model sim

modelsim sdf

hello every one ..

i use design compiler to synthesis, generate a netlist and SDF of a design written in verilog .. now wen tri to similute this file using model with sdf .. i get many errors saying tat many instances are missi..ports are missing and many more ..


Fatal: (vsim-SDF-3445) Failed to parse SDF file "design.sdf"

please soem let me know how can i simulate correctly ,.

suresh

sdf modelsim

Hi ,

Could you plese post first error in your transcript ?

with that I can give a better answer or type "verror <error_code>" on unix cmd line .

That will give elobarate answer .


Thanks & Regards
yln

vsim-sdf-3251

hello yln2k2

Thanks lot for ur reply the following are the errors shown in the transcript ..

# ** Error: (vsim-SDF-3251) ***.sdf(82452): Failed to find port 'D'.
# ** Error: (vsim-SDF-3251) ***.sdf(82453): Failed to find port 'D'.
# ** Error: (vsim-SDF-3251) ***.sdf(82454): Failed to find port 'D'.
# ** Error: (vsim-SDF-3251) ***.sdf(82455): Failed to find port 'D'.
# ** Error: (vsim-SDF-3251) ***.sdf(82456): Failed to find port 'D'.
# ** Error: (vsim-SDF-3251) ***.sdf(82457): Failed to find port 'D'.
# ** Error: (vsim-SDF-3251) ***.sdf(82458): Failed to find port 'D'.
# ** Error: (vsim-SDF-3251) ***.sdf(82459): Failed to find port 'D'.

i am using a older version of model .. is it making any prob .. becuase . it also says .. fatel error in parsing ..

suresh

modelsim sdf simulation

Hello Suresh ,

I did verror <errorcode> i got following info means

This is due to any of the following reason

1) There may be SDF syntax issue or The port may not be there in Entity or Module Defination ... Please check the same .
Try to ask your backend team whcih memory lib they used to generate SDF , try to goto that dir and pick the corresponding memory model that should solve the issue .

2) or IF you are annotation to wrong hierarchy too ....

Please let me know if you need any info ...

sim Message # 3251:
Either the specified port or the instance containing the port could
not be found in the design. Verify that the SDF file is being applied
at the correct level of the design.
[DOC: ModelSim User's Manual -
Standard Delay Format (SDF) Timing Annotation Chapter]

modelsim vsim sdf

hi,

it looks like you made a mistake during sourcing the .sdf file. In modelsim you must give in "Apply to Region" field these things

/the_instance_name/

the_instance_name is the same name you given for the top_level instantiation in testbench.

OR

you can type in modelsim shell the following format

vsim -sdftyp /the_instance_name/=the_sdf_file_name.sdf work.the_tb_filename.vhd

regards
vs21

vsim sdf

hello all

thanks a lot .. I was able to solve most of the problems '


suresh

sdf file modelsim

maybe modelsim does not support.

failed to find sdf file .sdf

Hi,
i think version of SDF matters here ,save sdf in 2.1 version this may solve your failures.

modelsim+sdf

in verilog,u can use the system task $sdf_annotate to include the sdf file..

sdf-3251

you must ensure the sdf matches your netlist.

modelsim sdf annotation

I met the same question.
Modelsim simulator donot support. when I use the NC-verilog, it is OK.

sdf modelsim compile

Timing simulation is best in NCsim

I am getting following error while simulating using SDF file.

# ** Error: C:\Documents and Settings\Administrator\Desktop\Verilog_design\synth\dff\netgen\par\d_ff_timesim.v(769): Module 'X_IPAD' is not defined.
# ** Error: C:\Documents and Settings\Administrator\Desktop\Verilog_design\synth\dff\netgen\par\d_ff_timesim.v(775): Module 'X_BUF' is not defined.
# ** Error: C:\Documents and Settings\Administrator\Desktop\Verilog_design\synth\dff\netgen\par\d_ff_timesim.v(780): Module 'X_OPAD' is not defined.
# ** Error: C:\Documents and Settings\Administrator\Desktop\Verilog_design\synth\dff\netgen\par\d_ff_timesim.v(786): Module 'X_OBUF' is not defined.
# ** Error: C:\Documents and Settings\Administrator\Desktop\Verilog_design\synth\dff\netgen\par\d_ff_timesim.v(791): Module 'X_IPAD' is not defined.
# ** Error: C:\Documents and Settings\Administrator\Desktop\Verilog_design\synth\dff\netgen\par\d_ff_timesim.v(797): Module 'X_BUF' is not defined.
# ** Error: C:\Documents and Settings\Administrator\Desktop\Verilog_design\synth\dff\netgen\par\d_ff_timesim.v(802): Module 'X_IPAD' is not defined.
# ** Error: C:\Documents and Settings\Administrator\Desktop\Verilog_design\synth\dff\netgen\par\d_ff_timesim.v(808): Module 'X_BUF' is not defined.
# ** Error: C:\Documents and Settings\Administrator\Desktop\Verilog_design\synth\dff\netgen\par\d_ff_timesim.v(814): Module 'X_BUF' is not defined.
# ** Error: C:\Documents and Settings\Administrator\Desktop\Verilog_design\synth\dff\netgen\par\d_ff_timesim.v(827): Module 'X_SFF' is not defined.
# ** Error: C:\Documents and Settings\Administrator\Desktop\Verilog_design\synth\dff\netgen\par\d_ff_timesim.v(833): Module 'X_BUF' is not defined.
# ** Error: C:\Documents and Settings\Administrator\Desktop\Verilog_design\synth\dff\netgen\par\d_ff_timesim.v(839): Module 'X_BUF' is not defined.

# Optimization failed
# Error loading design



Please help...