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Gate level simulation: Quaries on simulation issues

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satyakumar

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issues for gate level simulation

Hi to all,

I have a basic question regarding gate level simulation, I generated netlist for some design in synopsys based on UMC lib. But i don't want to use VCS instead i want to simulate with NCsim or modelsim. My question is how to setup libraries or these tools support synopsys DB and netlist files, if so please give me some detailed explianation.

Thanks to all.
 

edif testbench site:edaboard.com

U can't use library format in .db format, For a mapped library there will be a .v or .vhd file will be there , U hav to compile it with NCsim and add as a library,
The library will contains the all cells and its functionality,
And more U have to add SDF file (genrated by SYNTHESIS TOOL) for Backannotation.

Then U can compile it.
 

gate level simulation issues

ya u have corelib.v in the synopsys directory(in packages wat u r using like 90nm or 65nm or so)
compile this .v file with ur netlist.v and testbench.v file. it works
 

syntax for gate level simulation

Thanks to all

Is it posible to use EDIF file generated by synopsys synthesis tools?
 

ncsim edif file

Hi satyakumar !!!

If you want use the NCSim, simulation netlist, You neseccary genrating SDF

If you want to use the NCSim, for netlist simulation. You need SDF file generating.
One attached in testbench
initial
$sdf_annotate ("<name>.sdf", <instance of element>);

in command line write next =>
ncverilog +gui +access+rwc -v <library name>.v testbench.v <netlist name>.v
 

Hi to all

I tried to do gate level simulation in modelsim with DC generated netlist.v and sdffile.sdf along with corelib.v. But im unable to simulate, it gives "unable resolve instance U5 in sdffile.v" like wise it gives for all instances in sdffile. I looked in sdffile and netlist file the instances are corectly defined, but im not understanding why this error coming. I opened the corelib.v it has just module defination for the instances used in netlist but it doesn't contain any relation between input and outputs. Is there any problem with corelib.v or any other file i need to include

Thanks to all

Added after 3 minutes:

Hi shurik

I tried using NCsim also, the sdf_annotate command it is not taking and what type library.v i need to give, I have only UMClib.v which contains only module definations but no relations between i/p and o/p
 

Hi
There shouldn't be any problems with corelib.v bcos u have used that library(or package) to generate ur netlist.
one problem may be ur source code may have not synthesized to the netlist u desired.
this is often a problem with me also.
writing sybthesizable code is far difficult than simulatable code
i don't think SDF is necessary to simulate the netlist.
 

Hi srinivas

I used umc.db library and mydesign.v file for synthesis in DC, i didn't used any other verilog lib. Do i need to include any verilog lib , in my lib folder only one library file which contains module definations with out functionality. And in generated netlist only module instances are there, so, is this a problem of the synthesis procedure.

Thanks
 

hi
wat u have used is right for synthesis.
hope u have used the link lbrary also in synthesis.
try without including sdffile
the corelib file doesn't consist any input or output's.
note tat ur netlist input outputs are same as the source file i/o's.only logic inside will be converted and thisconversion togates wil be based on the library(corelib) so itdoesn't have any input output declarations.
 

Hi

adder.v is my input design file.

module adder(inA,inB,inC,sum,cary);
input inA,inB,inC;
output sum,cary;
sum <= ina^inB^inC;
cary <= (inA&inB)|(inC&inB)|(inA&inC);
endmodule;

after synthesis the generated netlist

module adder(inA,inB,inC,sum,cary);
input inA,inB,inC;
output sum,cary;

HDEXORDL2 U4(.A(inA), .B(inB), .C(inC), .Z(sum));
HD... for and gate
......
endmodule;

in generated SDF timing information is present for instance HDEXORDL2,.......
But the HDEXORDL2, ...for remaing instances there is no instances are present inorder to define the functionality of generted netlist. So in simulation it is giving the same error. In which lib or file this info is present.

Thanks
 

sum <= ina^inB^inC;
cary <= (inA&inB)|(inC&inB)|(inA&inC);
if this is ur code
u have to put it in an always.
regarding the inferred module it may be an adder which is an inbuilt function in the library.
 

it is = not <=. there might be syntax error here in msges. Im trying to highlight the procedure. every thing worked fine only prob is at the gate level simulation
 

satyakumar said:
Hi shurik

I tried using NCsim also, the sdf_annotate command it is not taking and what type library.v i need to give, I have only UMClib.v which contains only module definations but no relations between i/p and o/p
Click to expand...

Hi satyakumar !
Is it library have enclose all models of standart cells ?
That this that most library!!!!!
 

what is the full set of libraries that are needed to simulate a gate-level netlist ?
 

Hi omara
For gate level simulation corelib.v, netlist and sdf file generated by synthesis tool for particular techmology and testbench is needed.
 

satyakumar said:
Hi omara
For gate level simulation corelib.v, netlist and sdf file generated by synthesis tool for particular techmology and testbench is needed.
Click to expand...

and how to get the corelib.v file ?
 

satyakumar said:
corelib.v comes with technology library.
Click to expand...

No .. it doesn't by default .. I don't have it in my technology files .. it should be generated from the technology files by some means!
 

I think it can be done using synopsys design compiler. Read tech.db file and write verilog, but i never done.
 

Hi,
would it be possible to do a gatelevel simulation for a xilinx/ altera cpld based designs using ncsim ? i've generated a netlist and am using ncvhdl. could someone tell the procedure for it ?
 

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