Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Problem with co-simulation

Status
Not open for further replies.
Y

yesme@

Member level 1
Joined
Jun 21, 2005
Messages
38
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,570
I have got an error message when doing a co-simulation (SystemC & Verilog HDL (netlist)):

# ** Fatal: (vsim-3681) No type information available for SystemC primitive channel 'signal_84' connected to HDL signal '.testbench.test_wrapper.node_gate_i.OP_DATA_ack'.
# Each SystemC channel/port connected to HDL signals should be constructed
# using an explicit name that matches the name of the object in the C++ source code.

I've verified all ports' declarations and they are OK. I don't understand what happen.

Help me pls !
 

yesme@ said:
I have got an error message when doing a co-simulation (SystemC & Verilog HDL (netlist)):

# ** Fatal: (vsim-3681) No type information available for SystemC primitive channel 'signal_84' connected to HDL signal '.testbench.test_wrapper.node_gate_i.OP_DATA_ack'.
# Each SystemC channel/port connected to HDL signals should be constructed
# using an explicit name that matches the name of the object in the C++ source code.

I've verified all ports' declarations and they are OK. I don't understand what happen.

Help me pls !
Click to expand...
Can you post some code to show how you've declared "signal_84" in SystemC side and what's the type of:

testbench.test_wrapper.node_gate_i.OP_DATA_ack'

I've not done too much SystemC but error looks fairly clear - an obj/channel is accessed before being constructed or some thing like that.

Regards
Ajeetha, CVC
www.noveldv.com
 

OP_DATA_ack is an input port of node_gate.h module and it is declared as follow:

sc_in < sc_logic > OP_DATA_ack;

In the Verilog HDL file, from which we get the netlist, the OP_DATA_ack is a std_logic input.
 

Hi,

Did you find the solution to this problem ?
I have been struggling with the same for days now, so any help would be greatly appreciated.

Thanks,

Z.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top