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Is it necessary to do post layout simulation after STA?

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albred

albred

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gatesim pre layout post layout

The post layout simulation is one part of IC design flow, while the function verification has been done by pre-layout simulation.
If the design has pass pre-layout simulation and post-layout STA, is it necessary to do post layout simulation for the design?
What's the issues that can't be detected by STA? What's the limitation of STA?
It's said that STA can't check the asynchronous timing?
 

Hi

In STA you chek all the paths wether they meet the timming or not........ what you dont check is the functionality of the chip......
In post layout simulation you do a functional simulation with the knowledge of delay values
 

Hi neo_chip,
I should add that the function verification has been done by pre-layout simulation.
 

ya......... you do that
But you do that without an accurate delay values(you do it with delay models).....
The sdf file you get after p&r contains exact delay values............ doing a functional simulation with this sdf(post layout simulation) file, will give you more accurate results
 

STA is static timing analysis.
You perform STA in post-synthesis and also in post-layout.
In post-layout, you usually perform STA and SPA.
SPA is power analysis, especially for submicron ASIC.
The purpose of STA in post-synthesis is merely check if your setup and hold time are violated or not.
Functional simulation is not STA!
All HDL simulators can verify functionalities without you needing to elaborate and synthesize.

The purpose of STA, especially post-synthesis and post-layout is for timing closure.
STA performed at post-synthesis is based on cell library delay models.
STA performed at post-layout is based on the parastic circuit extraction from routes, usually in SDF.

STA performed in post-layout is only required if you work on semi-custom ASIC only. You don't do this for prototyping with FPGA.
 

Short answer is YES.

STA could be wrong if you set any constraints incorrectly. You need to run some gatesim to at least confirm it.

It's like your zero-delay gatesim to verify the funtionality even though your formal verification passes because some contraints when you do the formal verification might be wrong.
 

stevepre said:
Short answer is YES.

STA could be wrong if you set any constraints incorrectly. You need to run some gatesim to at least confirm it.

It's like your zero-delay gatesim to verify the funtionality even though your formal verification passes because some contraints when you do the formal verification might be wrong.
Click to expand...

It seems like checking the design using as more different methods as possible to reduce the risk, because none method is perfect:D
 

Functional verification is done before synthesis.

STA is done to check the if the timings are met as per the assumptions we have made (in the form of constraints for STA).

But we also do gate level simulations... There are several reasons for this :
1. Your assumptions / constraints during STA could be wrong (over constrained or under constrained)
2. Asynchronous paths are not analyzed during STA
3. If there are any analog-ish IPs in the design , again these are not analyzed during STA. Analog-ish could mean PLL, various kinds of memories, some customized system control circuitry ... etc

Other than these there is no other technical reason for doing simulations after STA (with back annotation (sdf data)). It is also a confidence building exercise because if anything goes wrong beyond this phase, it will be a very costly affair (in terms of $$ & time too) to come back and fix it.

Best Regards,
Harish
https://hdlplanet.tripod.com
https://groups.yahoo.com/group/hdlplanet
 
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    iyama

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if your design flow include LEC to compare RTL and netlist, then

I think post simulation is not necessary.


best regards





albred said:
The post layout simulation is one part of IC design flow, while the function verification has been done by pre-layout simulation.
If the design has pass pre-layout simulation and post-layout STA, is it necessary to do post layout simulation for the design?
What's the issues that can't be detected by STA? What's the limitation of STA?
It's said that STA can't check the asynchronous timing?
Click to expand...
 

Running post layout gate simulation is necessary, if your constraints contains complicated multi-cycle path.
 

Hi,

We cannot be sure that STA is done properly as it cannot be checked. For example, we can say "set_input_delay 5ns -min", but this is translated from specification, and maybe it is incorrectly translated, or maybe the testbench is wrong (catch a testbench error, and this can be significant also).

Regards,
Eng Han
 

albred said:
The post layout simulation is one part of IC design flow, while the function verification has been done by pre-layout simulation.
If the design has pass pre-layout simulation and post-layout STA, is it necessary to do post layout simulation for the design?
What's the issues that can't be detected by STA? What's the limitation of STA?
It's said that STA can't check the asynchronous timing?
Click to expand...

if you want to find the "Timing violation" , i think no need!
if you want to find the "behavioal error " , i think yes !
 

Uou can use Verplex to compare the netlist before and after layout, if no error found a STA pass would be goo enough, but make sure your constraint file is good enough including chip boundary.
 

but i wonder,
in some design, when the frequency of clock is very low, is it need STA?
is it enough only to do post-simulation ?
 

STA only can check the timing path for design.
post-layout simulation can check timing and logic check.
 

STA is based on the applied constraint that developed by designers, which is not verified. so psotlayouot simulation is necessary.
 

I have the same question.
If my design is constrainted carefully and all of the path is passed, is the post-synthesis simuation neccessary ?
 

Say your design is fully synchronous and you have perfect STA and Formal-Verification constraints then I would say you don't need a SDF sim.

But I have never seen this premises in any of my projects.

SDF sim can catch bugs in the STA script and is a good way of checking that inter-block asyc data communication is working as specified. Moreover it gives you a warm feeling that things are working before tape-out

cheers
 

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