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Explain what is 'task' in Verilog

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hariharan4000

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Hi
what is 'task' in verilog.
R they used only for test benches or can be used in design?
plz explain with simple verilog code eg.. a simple clock generator or sync d- flipflop.


regards
Hari
 

Re: TASK -- Verilog

hi hariharan,
A task in verilog is used to write a sub-routine within a module. Here is an example code which performs 3 bit counter,

module counter(c,clk);
output reg c[0:3];
input clk;
c[0:3]<=3'b000;
count(c);
end

task c;
inout c[0:3];
begin
c=c+1;
end
endtask
endmodule

i did not simulated it. there may be some error. But this example can give you a clear idea of using 'TASK'.

with regards
sathish kumar
 

Re: TASK -- Verilog

Hi hari,
Tasks are used only in testbench. But functions can use in design.
 

Re: TASK -- Verilog

Hi
Task is never used in design
Pnly used in TBs
 

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