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Any DC Timing Optimization technique?

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yuenkit

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timing optimization techniques

Hi,

Where can we find the info regarding DC timing optimization technique?

I am currently handling a design, which has a very long path. The long path cause timing violation. This is an IP, so it's hard for me to introduce additional register inside.

So I wish to know some DC timing optimization techniques which I hope it can solve timing problem.

Thanks.
 

you can try borrow slack from another stage using
dc command -- pipeline_register
 

get timing path and do grouping and incremental compile.
 

Several ways to solve timing problem
1. Increase cell driving capability. E.G. from BUFX1 to BUFX4.
2. Insert buffers or invert pairs.
3. Split heavy load sub-path. (Relax the bottleneck)
4. Delay the clock wire to the destination cell to borrow timing from next stage.
Take a look at
https://www.nandigits.com/timing_eco.htm

Nandy
www.nandigits.com
Netlist Debug/ECO in GUI mode.
 

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