david119
Junior Member level 2
lattice generate testbench
Hi everyone,
I'm using lattice semiconductor's ispLEVER starter software to work on an FPGA project. This is my first FPGA project and I don't know how to run a functional simulation to check the logic using the VHDL template.
I've put the VHDL template that the software generated in word and attached it. There are three inputs a clock, reset, and latch. And there are 29 outputs. The output is a binary form of time 0:00:000. Just like a stopwatch.
My problem is that I don't know what to add to the VHDL template. I need to generate an ongoing clock signal followed by periodic reset and latch signals.
Any help would be greatful
Thanks in advance
Hi everyone,
I'm using lattice semiconductor's ispLEVER starter software to work on an FPGA project. This is my first FPGA project and I don't know how to run a functional simulation to check the logic using the VHDL template.
I've put the VHDL template that the software generated in word and attached it. There are three inputs a clock, reset, and latch. And there are 29 outputs. The output is a binary form of time 0:00:000. Just like a stopwatch.
My problem is that I don't know what to add to the VHDL template. I need to generate an ongoing clock signal followed by periodic reset and latch signals.
Any help would be greatful
Thanks in advance
