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How to implement the primitive " tranif0 or tranif1 &q

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Matrix_YL

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tranif1

HI all

The primitive tranif0 and tranif1 are not support by Xilinx for synthesable design ,but my design needed to implement the function of primitive "tranif0 or tranif1 "

for example if C is 1 , A <=>B(bidirectional transfer ) , else C is 0
disabled bidrectional transfer )

thank you !
 

tranif0

These primitives are not synthesizable because these transistors are not available in Xilinx or any other FPGA. Xilinx and other FPGAs do not have such primitive transistors in them. You can only design systems using the blocks that are present in them.

To solve your problem, you will have to design a bidirectional register using verilog and implement it. If you are using the A and B ports as inputs and outputs to a module, you will have to declare them as inout or buffer. Also avoid multiple drivers for a signal.
 

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