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50 ohm Dummy Load With 50dB Attenuator

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OnurCan

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Hi,
I am designing a 50 ohm 10 watts dummy load for 100-1000MHz frequency range. The signal strength should not exceed -10dBm. The load must be able to dissipate 5 watts minimum, that is +37dBm. The output to the test equipment must be no more than -10dBm. So I need an attenuation of 47dB but to make it easy lets say 50dB.

After the load as you can see in the schematic picture there is 3 different attenuators. The first one is 20dB attenuator for 5W dissipation, second one is 20dB-50mW dissipation and the last one is 10dB-50mW dissipation. You can see the values of the resistors on the schematic picture.

Specification for the PCB board:

Trace thickness : 0.036mm

Substrate height : 0.8mm

Trace Width : 1.5mm for 50ohms

Substrate Dielectric : 4.3

One thing that I couldn't figure out here is the width of the tracks when routing the attenuators as you can see some of them routed with a narrow line. Should it be as thick as 50ohms or something different considering the values, I don't know this because I have never seen it before. Long story short I need help with the circuit and routing the microstrip to have a good impedance match.
sche.PNG
Schematic of the circuit is something like that.
I have a problem with appliying this to a PCB board I know I should arrange R3-R6 symmetrically around the input connector, keeping the current path loops as short as physically possible. But I couldn't figure out myself. If you guys can guide me with placing the resistors and routing my problem will be solved.

I did something on my own you can check it below but I am pretty sure that is not the best way to do it. So waiting for your help.
br1.PNG
Thank you for your time.
 

I would place resistors 1-4 very close to the left pad of At1.1. Use 50 Ohm track from SMA connector to resistors 1-4. Place one pad of resistors 1-4 on the 50 Ohm track. Since your substrate is rather thick, the main parasitic effect is series inductance. Place the resistor pad on the main track will reduce the parasitic inductance to be the minimum. If the resistors are of metal thin film type, another trick to reduce parasitic inductance is to mount the resistor upside down, i.e. let the metal film side be down.
 
I would place resistors 1-4 very close to the left pad of At1.1. Use 50 Ohm track from SMA connector to resistors 1-4. Place one pad of resistors 1-4 on the 50 Ohm track. Since your substrate is rather thick, the main parasitic effect is series inductance. Place the resistor pad on the main track will reduce the parasitic inductance to be the minimum.

br2.PNG

You mean something like this?

Doesn't the signal need to reach all of them at the same time? I mean resistor 1-4.
 

Doesn't the signal need to reach all of them at the same time? I mean resistor 1-4.
Ideally yes, but any real layout has non-zero dimensions and respectively some parasitic elements.

A star topology should use Z=250 ohm strip lines, respectively 125 ohms for the stub connecting two resistors. Your original layout doesn't seem to achieve matched impedances for the stubs. An exact simulation would also refer to s-parameter models of the resistors.
 
Ideally yes, but any real layout has non-zero dimensions and respectively some parasitic elements.

A star topology should use Z=250 ohm strip lines, respectively 125 ohms for the stub connecting two resistors.

How would you do it as a star shaped topology? Could you show me to just give me an idea?
 

Doesn't the signal need to reach all of them at the same time? I mean resistor 1-4.

That is the time domain view, but 1GHz is not that critical (at these dimension we discuss here).

Another aspect to consider is the shunt capacitance of your routing plus pads plus resistors to ground, which will introduce mismatch. And your star topology also had unnecessary series line length = series L. I would expect all this to be a much larger effect.
 

View attachment 159576

You mean something like this?

Doesn't the signal need to reach all of them at the same time? I mean resistor 1-4.

This layout looks better. You may also reduce the size of resistors At2.2 and At3.2, since the power has been greatly reduced by the first attenuator.
 

R1 to R4 placement is near to a star topology, but with inappropriate stub impedances.

Problem is that you can't micro strip lines above 125 to 135 ohms with the used FR4 substrate. This restricts the options to make a distributed resistor layout with matched transmission line stubs. For the intended frequency range up to 1000 MHz, stubs shorter than 20 mm can be modelled as parasitic parallel capacitance or series inductance, depending on the mismatch sign.

I would start with the post #3 topology, may be extend it to a staggered transmission line, 50 ohms between connector and first resistor tap, 83 ohms between first and second resistor tap, minimal stubs for 250 ohms series resistors.
 

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