+ Post New Thread
Results 1 to 4 of 4
  1. #1
    Member level 3
    Points: 2,691, Level: 12
    Achievements:
    7 years registered

    Join Date
    May 2007
    Location
    Germany
    Posts
    63
    Helped
    3 / 3
    Points
    2,691
    Level
    12

    A Code issue in Verilog

    Hi,
    Please see the code below:

    Code:
    module ha ( input   a, b,
                output  sum, cout);
     
      assign sum  = a ^ b;
      assign cout = a & b;
    endmodule

    Code:
    module my_design 
      #(parameter N=4) 
        (  input [N-1:0] a, b,
          output [N-1:0] sum, cout);
     
    
      generate 
        for (i = 0; i < N; i = i + 1) begin
              ha u0 (a[i], b[i], sum[i], cout[i]);
        end
      endgenerate
    endmodule
    As in above example, we saw that ha was generated N times. The issue that I can not understand is, all the generated instances will get an instance name as u0. But this code actually works. But doesn't the instance names should be unique? How come this is working, and that works actually!
    No, I don't have engine !!!

    •   AltAdvertisement

        
       

  2. #2
    Advanced Member level 5
    Points: 38,490, Level: 47
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,960
    Helped
    2051 / 2051
    Points
    38,490
    Level
    47

    Re: A Code issue in Verilog

    the generate gives each instance a unique path



    •   AltAdvertisement

        
       

  3. #3
    Super Moderator
    Points: 265,394, Level: 100
    Awards:
    1st Helpful Member

    Join Date
    Jan 2008
    Location
    Bochum, Germany
    Posts
    46,367
    Helped
    14113 / 14113
    Points
    265,394
    Level
    100

    Re: A Code issue in Verilog

    The compiler assigns unique hierarchical names for unnamed generates, review LRM 27.6.



    •   AltAdvertisement

        
       

  4. #4
    Member level 3
    Points: 2,691, Level: 12
    Achievements:
    7 years registered

    Join Date
    May 2007
    Location
    Germany
    Posts
    63
    Helped
    3 / 3
    Points
    2,691
    Level
    12

    Re: A Code issue in Verilog

    Thanks for replies.
    Actually the source of my confusion is as follows.

    Here is a generate code:

    Code:
    generate
        genvar row;
        for (row=0;row<5;row=row+1) begin : I_ROW
         AND CU (.a(row),.b(row),.c(row));
          genvar j;
          for (j=0;j<8;j=j+1) begin : CELL
            OR LA (.a(j),.b(j),.c(j)), 
          end   
        end
      endgenerate
    As it might be seen that there are two for loops. I wanted to force c outputs in OR LA loop. I also checked the following thread:
    https://www.edaboard.com/showthread....System-Verilog

    but confusion is, how to deal with this double for loop.

    @FvM @TrickyDicky @dave_59
    No, I don't have engine !!!



--[[ ]]--