sirnef
Newbie level 2
Hi,
I'm thinking of a project for an FPGA from Xilinx, where the camera data will be saved to the BRAM. I've got to calculate the buffers and other interfaces.
The camera interface with FIFO and BRAM will be connected to AXI Smartconnect component. In case of a 100 MHz clock, what data rate can I expect when writing and reading from BRAM?
I'm thinking of a project for an FPGA from Xilinx, where the camera data will be saved to the BRAM. I've got to calculate the buffers and other interfaces.
The camera interface with FIFO and BRAM will be connected to AXI Smartconnect component. In case of a 100 MHz clock, what data rate can I expect when writing and reading from BRAM?