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  1. #1
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    Switch size in a resistive trim network ?

    The picture shows resistive trim networks.
    I am using a 0.18um CMOS process.
    How should I choose the NMOS switch size (W/L) for the resistive network 1 and 2 ?
    What criteria decides the required ON resistance for the NMOS switches ?

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  2. #2
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    Re: Switch size in a resistive trim network ?

    Use minimum L, and choose the minimal W with the following conditions:
    - lowest gate voltage applied
    - slow-slow (SS) process
    - cold temperature (but maybe the hottest temp is also recommended to try)
    - select only the top device, switch off the lower ones
    - set Ron at least 10 times samller than R

    Use the same width for all switching devices is recommended.
    You can do it with both branch, network.
    If the sizes are too big you should increase the value of R or you can set a bit smaller width for the lower switches, or lower finger number, multiplication factor.
    "Try SCE to AUX." /John Aaron/



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  3. #3
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    Re: Switch size in a resistive trim network ?

    I recommend considering the resistor segment and the switch
    as the resistor-bank "unit cell", and repeating this as you make
    series / parallel arrangements.

    Switch Ron vs common mode is a secondary concern which
    might make you favor parallel links with the NMOS switches
    all at vssa! potential.

    Depending on sensitivities you might want to use greater
    than minimum L especially on links which could see near
    full rail voltage, to ensure that leakage remains negligible
    at fast*hot. I would not count on models showing you
    the range of leakage-floor and subthreshold leakage that
    production material eventually will.



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