Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Actually I set both existing and spec view. The following are constraints set on test_se
The existing_dft view is supposed to disable the clock-gating logic in scan-mode. But I don't know why it didn't work in this case?
Thank you for your explanation. Now I know what existing_dft really means.
About the DRC error, it turns out that I had multiple test modes in my design. And I didn't specify one before running dft_drc. The problem was solved by issuing the command
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.