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  1. #1
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    why is write delay low for 6T SRAM cell compared to 8T SRAM cell ?

    why is write delay low for 6T SRAM cell compared to 8T SRAM cell ?

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  2. #2
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    Re: why is write delay low for 6T SRAM cell compared to 8T SRAM cell ?

    Assuming that they are on the same technology (which
    you do not state) there's just the extra read-path load
    requiring additional slew time on write, to get to the
    positive feedback tipping point (plus margin).

    But SRAM technology node matters and comparing cell
    topologies across foundry or flow is pointless.

    8T is often applied as a radiation effects mitigation and
    even within a technology, you might see 8T cells use
    high-VT devices for total dose effects while 6T commercial
    designs might use LVT for speed (unless they are after
    low power foremost, then RVT).

    Don't ask for simple answers to questions like this. Do
    the reading. Details are everything.



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  3. #3
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    Re: why is write delay low for 6T SRAM cell compared to 8T SRAM cell ?

    not to mention that delay is only part of the equation. SRAM compilers usually offer low and high density designs (rings a bell?) as well as single and dual port. delay becomes rather irrelevant sometimes, depending on what the use case is.
    Really, I am not Sam.



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