dayana42200
Junior Member level 3
Hello everyone.
Currently, Im designing a processing element.
This design is synthesis in Xilinx ISE Design Suite 14.7 using Virtex 6 XC6VLX75T-2FF484.
I have problem on the timing analysis.
The is no setup time and hold time reported as shown below.
There is no slack for setup time and hold time.
During synthesis and implementation of the device, the is no warning and error.
Please. Could anyone help me?
Currently, Im designing a processing element.
This design is synthesis in Xilinx ISE Design Suite 14.7 using Virtex 6 XC6VLX75T-2FF484.
I have problem on the timing analysis.
The is no setup time and hold time reported as shown below.
There is no slack for setup time and hold time.
During synthesis and implementation of the device, the is no warning and error.
Please. Could anyone help me?