firasgany7
Junior Member level 1
Hi guys,
I designed a PLL, and I'm not getting to a locking state yet. I'm trying to debug the problem by observing the behavior of different signals.
It seems that I'm getting only Up Pulses and the behavior is periodic.
here is one that simulation that shows the periodic behavior of Up pulses:
do you suspect any problem with any device just by looking at this simulation?
thanks
I designed a PLL, and I'm not getting to a locking state yet. I'm trying to debug the problem by observing the behavior of different signals.
It seems that I'm getting only Up Pulses and the behavior is periodic.
here is one that simulation that shows the periodic behavior of Up pulses:
do you suspect any problem with any device just by looking at this simulation?
thanks