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Phase locked Loop Locking

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firasgany7

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Hi guys,

I designed a PLL, and I'm not getting to a locking state yet. I'm trying to debug the problem by observing the behavior of different signals.
It seems that I'm getting only Up Pulses and the behavior is periodic.

here is one that simulation that shows the periodic behavior of Up pulses:

pll_sim1.png


Plll_schematic.png

do you suspect any problem with any device just by looking at this simulation?


thanks
 

betwixt

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I would say something is wrong in the first block if the ring oscillator is working correctly. First check the oscillator is capable of running at the desired frequency so it isn't trying to keep pushing it higher but not succeeding.

Brian.
 

BigBoss

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The locking doesn't occur in few hundreds of nanosecond..It takes generally much more than this..
Observe the Output Frequency if there is a changing then increase your simulation stop time in according with..
 

dick_freebird

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To me it looks like the loop is unstable, but you really
do need a longer run time to be sure.

I recommend checking the VCO tune range first, it
looks like the vctrl needs to be nearly railed high in
order to flip from "up" to "down" charge pump control.
That it does so, indicates that at least the phase
detector works. But this may be a cause of "windup"
and loop instability.
 

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